The development of the EDVAC computer system of 1948 is often cited as the beginning of the computer era. Since that time, computer systems have evolved into extremely sophisticated devices, and computer systems may be found in many different settings. Computer systems typically include a combination of hardware (such as semiconductors, integrated circuits, programmable logic devices, programmable gate arrays, and circuit boards) and software, also known as computer programs.
The typical design methodology for integrated circuit designs—such as very large scale integrated (VLSI) circuits and application specific integrated circuits (ASICs)—is conventionally divided into the following three stages. First, a design capture step is performed using, for example, a high-level language synthesis package. Next, design verification is made on the resulting design. This includes simulations, timing analysis, and automatic test pattern generation (ATPG) tools. Finally, there is layout and eventual tape out of the device. The device is then tested, and the process may need to be reiterated one or more times until the desired design criteria are satisfied.
The design capture step is typically involves the specification of a logic circuit by a designer. A hardware description language (“HDL”) provides the designer with a mechanism for describing the operation of the desired logic circuit in a technology-independent manner using standard cells, which are physical layouts and timing behavior models for simple logic functions such as AND, OR, NOT, or FlipFlop. A large group of pre-designed standard cells is typically available as a standard cell library, which is typically provided at a nominal cost by the fabrication vendor who will eventually produce the actual chip. Examples of these standard cell libraries are available from fabrication vendors such as TSMC (Taiwan Semiconductor Manufacturing Company) or UMC (United Microelectronics Corporation).
Automated software tools available from companies such as Cadence Design Systems and Synopsys can take a netlist description of the integrated circuit, or netlist representing the desired logical functionality for a chip (sometimes referred to as a behavioral or register-transfer-level description), and map it into an equivalent netlist composed of the standard cells from a selected standard cell library. This process is commonly known as “synthesis.”
A netlist is a data structure representation of the electronic logic system that comprises a set of modules, each of which comprises a data structure that specifies sub-components and their interconnection. The netlist describes the way standard cells and blocks are interconnected. Netlists are typically available in Verilog, EDIF (Electronic Design Interchange Format), or VHDL (Very High Speed Integrated Circuit Hardware Design Language) formats. Other software tools available from companies such as Cadence or Avant! can take a netlist comprised of standard cells and create a physical layout of the chip by placing the cells relative to each other to minimize timing delays or wire lengths, then creating electrical connections (or routing) between the cells to physically complete the desired circuit. Once a netlist has been generated from the logic design, there are a number of commercially available silicon compilers, also called place and route tools, which are used to convert the netlist into a semiconductor circuit layout. The semiconductor circuit layout specifies the physical implementation of the circuit in silicon or other semiconductor materials.
Design verification involves verifying that the logic definition is correct and that the circuit implements the function expected by the designers. Typically, this involves timing analysis and simulation tools. The data representation in the logic design database may be reformatted as needed prior to use by the timing analysis and simulation tools. The design undergoes design verification analysis in order to detect flaws in the design. The design is also analyzed by simulating the device resulting from the design to assess the functionality of the design. If errors are found or the resulting functionality is unacceptable, the designer modifies the design as needed. These design iterations help to ensure that the design satisfies its requirements.
Other verification methods include generating software models of the logic circuit design and testing the software model of the design with designer-specified testcases. Because it is not possible to check every possible condition that may be generated in the actual logic design, faulty logic may remain because it would not have been exercised by any of the testcases. Errors in the logic design may remain undetected until the release of a product on the marketplace, where it may cause costly redesigns.
Formal verification is another way to check logic design prior to the fabrication of a device. Formal verification is a technique wherein a logic circuit is modeled as a state transition system, and specifications are provided for components in the system. One way in which specifications may be made is through the use of logic formulas. Each of the components in the logic design is specified, and all possible behaviors of the design may be exercised by a tool which confirms that these specifications are met.
The design verification phase typically involves sending commands as input to the simulated circuit and verifying that the output of the simulated circuit in response to the commands is correct and is in the correct order. Unfortunately, commands with identical data can be sent to the simulated circuit with no way to determine if responses to the commands occur in the correct order. Thus, test environments are currently unable to verify that circuits are processing all commands in the correct order during simulation, which delays the detection and correction of errors, lengthens the product development cycle, and increases the cost of the product.